This invention relates to programmable logic devices ("PLDs"), and more particularly to bit line sense amplifiers for PLDs.
Programmable logic devices are well known. Such a device frequently takes the form of an array of programmable interconnect elements. The array can be any size, including a single row, but it is not unusual for such an array to contain hundreds of rows and hundreds of columns. The array is based on a grid of orthogonal signal lines known as "bit lines" and "word lines". The programmable interconnect elements are typically erasable programmable read-only memories ("EPROMs"), such as electrically erasable programmable read-only memories ("EEPROMs") or ultraviolet erasable programmable read-only memories ("UVEPROMs"), although other types of programmable elements may be used. In a row of EPROMs extending in one direction, the gate of each EPROM is connected to a word line, while in an orthogonal row of EPROMs the drain of each EPROM is connected to a bit line. The source of each EPROM is connected to ground, typically through lines running parallel to the bit lines, although they could also run parallel to the word lines. The lines through which the sources are connected to ground, which may not actually be at ground potential, may be referred to as "common source lines", or just "source lines."
A user can "program" a desired bit in the array by placing a sufficient charge on the floating gate of the appropriate EPROM to prevent it from conducting even when its gate voltage (controlled by the word line) is high. Once the desired EPROMs have been programmed, a desired logical output can be obtained for a particular input to selected word lines.
One way of reading the output of the array is by sensing the status of each bit line with a circuit known as a sense amplifier, one of which is provided for each bit line. If none of the EPROMs connected to a particular bit line is conducting, the sense amplifier will indicate a high output (or a low if an inverting amplifier is used, as is typically the case). If any of the EPROMs is conducting, it will tend to bring the bit line voltage to ground, resulting in a low (or high) output.
One tends to think of the EPROMs as switches, so that if any EPROM is conducting, the bit line should be shorted to ground. However, each EPROM has impedance and, more importantly, capacitance, so that a conducting EPROM will have to discharge the capacitance of all of the non-conducting EPROMs connected to the same bit line. As a result, the bit line reaches ground faster if there are more EPROMs conducting (a state referred to as "super zero") than if only one is conducting ("weak zero"). Conversely, the transition from a super zero to a high state--i.e., from a state where many EPROMs are conducting to one where none is conducting--is also slow, because the capacitances of the EPROMs must be charged up from a relatively low initial potential, as compared to the transition from a weak zero state to a high state, where the capacitances of the same number of EPROMs must be charged, but from not quite so low an initial potential.
Many existing sense amplifiers are triggered to output a high or low signal based simply on a particular voltage level on the bit line. These sense amplifiers thus switch more slowly from the high state to the weak zero state than the from high state to the super zero state, and from the super zero state to the high state than from the weak zero state to the high state, because of the difference in elapsed time necessary to reach the switching voltage from the different states.
It would be desirable to be able to provide a sense amplifier having switching times that are substantially the same regardless of the initial state.
It would also be desirable to be able to provide circuitry for limiting the voltage swing on the bit line of a PLD to improve switching speed.